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SWRU543–January 2019
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Cortex
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-M4 Peripherals
Table 3-19. CFGCTRL Register Field Descriptions (continued)
Bit Field Type Reset Description
3 UNALIGNED R/W 0h
Trap on Unaligned Access
Unaligned LDM, STM, LDRD, and STRD instructions always fault
regardless of whether UNALIGNED is set.
0h = Do not trap on unaligned halfword and word accesses.
1h = Trap on unaligned halfword and word accesses. An unaligned
access generates a usage fault.
2 RESERVED R 0h
1 MANIPEND R/W 0h
Allow Main Interrupt Trigger
0h = Disables unprivileged software access to the SWTRIG register.
1h = Enables unprivileged software access to the SWTRIG register.
0 BASETHR R/W 0h
Thread State Control
0h = The processor can enter Thread mode only when no exception
is active.
1h = The processor can enter Thread mode from any level under the
control of an EXC_RETURN value.
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