AES Registers
www.ti.com
640
SWRU543–January 2019
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Advance Encryption Standard Accelerator (AES)
17.4.15 AES_KEY1_0 Register (Offset = 38h) [reset = 0h]
AES_KEY1_0 is shown in Figure 17-28 and described in Table 17-18.
Return to Summary Table.
Key (LSW for 128-bit key)
Figure 17-28. AES_KEY1_0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-18. AES_KEY1_0 Register Field Descriptions
Bit Field Type Reset Description
31-0 KEY R/W 0h
Key data
17.4.16 AES_KEY1_1 Register (Offset = 3Ch) [reset = 0h]
AES_KEY1_1 is shown in Figure 17-29 and described in Table 17-19.
Return to Summary Table.
Key ? Missing content here?
Figure 17-29. AES_KEY1_1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-19. AES_KEY1_1 Register Field Descriptions
Bit Field Type Reset Description
31-0 KEY R/W 0h
Key data