Timer Registers
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SWRU543–January 2019
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General-Purpose Timers
9.5.16 GPTMTBPMR Register (offset = 44h) [reset = 0h]
GPTMTBPMR is shown in Figure 9-20 and described in Table 9-24.
This register allows software to extend the range of the GPTMTBMATCHR when the timers are used
individually. This register holds bits 23:16 in the 16-bit modes of the 16/32-bit GPTM.
Figure 9-20. GPTMTBPMR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED TBPSMR
R-X R/W-0h
Table 9-24. GPTMTBPMR Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R X
7-0 TBPSMR R/W 0h
GPTM Timer B Prescale Match. This value is used alongside
GPTMTBMATCHR to detect timer match events while using a
prescaler.
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