Texas Instruments CC3235 SimpleLink Series - Cc32 Xx MCU and Wi-Fi; System-On-Chip

Pin
Mux
Flash SPI
Apps SPI
I2C
Audio Serial Port
Camera Interface
(8-bit Parallel)
SD Card I/F
(host)
GPIO A0
GPIO A1
GPIO A2
GPIO A3
UART A0
UART A1
ADC
Timer A
Timer B
GPT A0
Timer A
Timer B
GPT A1
Timer A
Timer B
GPT A2
Timer A
Timer B
GPT A3
APB
Bus
Bus Matrix
Multi-Layer
AHB
SRAM
Zero Wait State
4-Way Interleaved
Upto 256 Kb
Code + Data
ROM
64 Kb
Device Initialization
Bootloader
Driver Lib
ARM Cortex M4
80 MHz
ITM
SWJ-DP
SYSTICK
NVIC
AES DES/3DES SHA/MD5 CRC
HW Cryptography Accelerator
µDMA
ARCM
Apps Subsystem
Power-Reset-Clock
Controller
BridgeBridge
Top Level Bus
Pad Config Reg
ADC Control Reg
Device Config
GPRCM
Power-Reset-Clock
Global Controller
Always-ON Core Domain
Hibernate Controller
RTC counter + alarm
Pad Monitor
Wake Up Sequencer
DCDC Control
32 KHx XOSC DIG DCDC ANA DCDC PA DCDC
Supply Monitor32 KHz RC OSC
Low Phase Noise
Oscillator (40MHz)
IcePick
Pin Mux
DFT TAP
SoC TAP
MCU PLL WLAN PLL
802.11bgn Radio
802.11bgn Baseband
802.11bgn MAC
Application Protocols
TLS/SSL
UDP/TCP
IP
Supplicant
WiFi-Driver
Peripheral
Clocks & Resets
240 MHz, 80 MHz, 40 MHz
Always-ON
Core Domain
1.8 V Analog
Domain
Always-ON VBAT Domain
Level Shifters
DIG_PORZ (Digital Power-On Reset)
32 KHz
SYS
ICODE DCODE
2-W
4-W
SimpleLink Subsystem
2-wire/4-wire
pinout select
SOP [2:0]
240 MHz
80 MHz
40 MHz
480 MHz
XTAL
40MHz
Supply Input
2.1V ± 3.6 V /
1.85 V Regulated
XTAL
32.765
KHz
nRESET
Complete Chip Reset
CC3220 MCU + WiFi System-On-Chip
TM
TM
TM
www.ti.com Architecture Overview
41
SWRU543–January 2019
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Architecture Overview
1.2 Architecture Overview
Figure 1-1 shows the Internet-on-a chip.
Figure 1-1. CC32xx MCU and Wi-Fi
®
System-on-Chip