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Camera Registers
501
SWRU543–January 2019
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Parallel Camera Interface Module
14.6.4 CC_IRQENABLE Register (Offset = 1Ch) [reset = 0h]
CC_IRQENABLE is shown in Figure 14-12 and described in Table 14-7.
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The interrupt enable register enables or disables the module internal sources of interrupt on an event-by-
event basis (CCP and parallel mode).
Figure 14-12. CC_IRQENABLE Register
31 30 29 28 27 26 25 24
RESERVED
R/W-0h
23 22 21 20 19 18 17 16
RESERVED FS_IRQ_EN LE_IRQ_EN LS_IRQ_EN FE_IRQ_EN
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
RESERVED FSP_ERR_IRQ
_EN
FW_ERR_IRQ_
EN
FSC_ERR_IRQ
_EN
SSC_ERR_IRQ
_EN
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED FIFO_NOEMPT
Y_IRQ_EN
FIFO_FULL_IR
Q_EN
FIFO_THR_IR
Q_EN
FIFO_OF_IRQ_
EN
FIFO_UF_IRQ_
EN
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-7. CC_IRQENABLE Register Field Descriptions
Bit Field Type Reset Description
31-20 RESERVED R/W 0h
19 FS_IRQ_EN R/W 0h
Frame Start Interrupt Enable
0h = Event is masked
1h = Event generates an interrupt when it occurs
18 LE_IRQ_EN R/W 0h
Line End Interrupt Enable
0h = Event is masked
1h = Event generates an interrupt when it occurs
17 LS_IRQ_EN R/W 0h
Line Start Interrupt Enable
0h = Event is masked
1h = Event generates an interrupt when it occurs
16 FE_IRQ_EN R/W 0h
Frame End Interrupt Enable
0h = Event is masked
1h = Event generates an interrupt when it occurs
15-12 RESERVED R/W 0h
11 FSP_ERR_IRQ_EN R/W 0h
FSP code Interrupt Enable
0h = Event is masked
1h = Event generates an interrupt when it occurs
10 FW_ERR_IRQ_EN R/W 0h
Frame Height Error Interrupt Enable
0h = Event is masked
1h = Event generates an interrupt when it occurs
9 FSC_ERR_IRQ_EN R/W 0h
False Synchronization Code Interrupt Enable
0h = Event is masked
1h = Event generates an interrupt when it occurs
8 SSC_ERR_IRQ_EN R/W 0h
False Synchronization Code Interrupt Enable
0h = Event is masked
1h = Event generates an interrupt when it occurs