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I2C Registers
247
SWRU543–January 2019
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Inter-Integrated Circuit (I
2
C) Interface
7.3.16 I2CSDR Register (Offset = 808h) [reset = 0h]
I2CSDR is shown in Figure 7-29 and described in Table 7-20.
Return to Summary Table.
NOTE: This register is read-sensitive. See the register description for details.
This register contains the data to be transmitted when in the slave transmit state, and the data received
when in the slave receive state. If the RXFIFO bit or TXFIFO bit are enabled in the I2CSCSR register,
then this register is ignored and the data value being transferred from the FIFO is contained in the
I2CFIFODATA register.
NOTE: Best practice recommends that an application should not switch between the I2CSDR
register and TX FIFO, or vice versa for successive transactions.
Figure 7-29. I2CSDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED DATA
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-20. I2CSDR Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-0 DATA R/W 0h
Data for Transfer
This field contains the data for transfer during a slave receive or
transmit operation.
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