Texas Instruments CC3235 SimpleLink Series - DMA_CHMAP1 Register

Register Description www.ti.com
152
SWRU543–January 2019
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Direct Memory Access (DMA)
4.3.4.20 DMA_CHMAP1 Register (offset = 514h) [reset = 0h]
DMA_CHMAP1 is shown in Figure 4-26 and described in Table 4-30.
Each 4-bit field of this register configures the DMA channel assignment.
Figure 4-26. DMA_CHMAP1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH15SEL_n CH14SEL_n CH13SEL_n CH12SEL_n
R/W-0h R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH11SEL_n CH10SEL_n CH9SEL_n CH8SEL_n
R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 4-30. DMA_CHMAP1 Register Field Descriptions
Bit Field Type Reset Description
31-28 CH15SEL_n R/W 0h
DMA channel 15 source select
27-24 CH14SEL_n R/W 0h
DMA channel 14 source select
23-20 CH13SEL_n R/W 0h
DMA channel 13 source select
19-16 CH12SEL_n R/W 0h
DMA channel 12 source select
15-12 CH11SEL_n R/W 0h
DMA channel 11 source select
11-8 CH10SEL_n R/W 0h
DMA channel 10 source select
7-4 CH9SEL_n R/W 0h
DMA channel 9 source select
3-0 CH8SEL_n R/W 0h
DMA channel 8 source select