Register Map
www.ti.com
90
SWRU543–January 2019
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Cortex
®
-M4 Peripherals
3.3.1.6 DIS_0 to DIS_6 Register (offset = 180h to 198h) [reset = 0h]
DIS_0 to DIS_6 is shown in Figure 3-6 and described in Table 3-9.
The DISn registers disable interrupts. Bit 0 of DIS0 corresponds to Interrupt 0; bit 31 corresponds to
Interrupt 31. Bit 0 of DIS1 corresponds to Interrupt 32; bit 31 corresponds to Interrupt 63. Bit 0 of DIS2
corresponds to Interrupt 64; bit 31 corresponds to Interrupt 95. Bit 0 of DIS3 corresponds to Interrupt 96;
bit 31 corresponds to Interrupt 127. Bit 0 of DIS4 corresponds to Interrupt 128; bit 31 corresponds to
Interrupt 159. Bit 0 of DIS5 corresponds to Interrupt 160; bit 31 corresponds to Interrupt 191. Bit 0 of DIS6
corresponds to Interrupt 192; bit 7 corresponds to Interrupt 199.
NOTE: This register can only be accessed from privileged mode.
Figure 3-6. DIS_0 to DIS_6 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INT
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 3-9. DIS_0 to DIS_6 Register Field Descriptions
Bit Field Type Reset Description
31-0 INT R/W 0h
Interrupt Disable EN5 (for DIS5) register; EN6 (for DIS6) register
0h (R) = On a read, indicates the interrupt is disabled.
1h (W) = On a write, no effect.
1h (R) = On a read, indicates the interrupt is enabled.