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Register Description
143
SWRU543–January 2019
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Direct Memory Access (DMA)
4.3.4.11 DMA_ENASET Register (offset = 28h) [reset = 0h]
DMA_ENASET is shown in Figure 4-17 and described in Table 4-21.
Each bit of the DMAENASET register represents the corresponding DMA channel. Setting a bit enables
the corresponding DMA channel. Reading the register returns the enable status of the channels. If a
channel is enabled but the request mask is set (DMAREQMASKSET), then the channel can be used for
software-initiated transfers.
Figure 4-17. DMA_ENASET Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLR_n
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 4-21. DMA_ENASET Register Field Descriptions
Bit Field Type Reset Description
31-0 CLR_n R/W 0h Channel [n] Enable Set.
Bit 0 corresponds to channel 0.
A bit can only be cleared by setting the corresponding CLR[n] bit in
the DMAENACLR register or when the end of a DMA transfer
occurs.
0h = DMA Channel [n] is disabled.
1h = DMA Channel [n] is enabled.
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