SPI Registers
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SWRU543–January 2019
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SPI (Serial Peripheral Interface)
8.6 SPI Registers
Table 8-6 lists the memory-mapped registers for the SPI. All register offset addresses not listed in Table 8-
6 should be considered as reserved locations, and the register contents should not be modified.
Table 8-6. SPI Registers
Offset Acronym Register Name Section
10h SPI_SYSCONFIG System Configuration Section 8.6.1
114h SPI_SYSSTATUS System Status Section 8.6.2
118h SPI_IRQSTATUS Interrupt Status Section 8.6.3
11Ch SPI_IRQENABLE Interrupt Enable Section 8.6.4
128h SPI_MODULCTRL Module Control Section 8.6.5
12Ch SPI_CHCONF Channel Configuration Section 8.6.6
130h SPI_CHSTAT Channel Status Section 8.6.7
134h SPI_CHCTRL Channel Control Section 8.6.8
138h SPI_TX Channel Transmitter Section 8.6.9
13Ch SPI_RX Channel Receiver Section 8.6.10
17Ch SPI_XFERLEVEL Transfer Levels Section 8.6.11
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