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SPI Registers
301
SWRU543–January 2019
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SPI (Serial Peripheral Interface)
8.6.8 SPI_CHCTRL Register (offset = 134h) [reset = 0h]
SPI_CHCTRL is shown in Figure 8-27 and described in Table 8-14.
This register enables the channel and defines the extended clock ratio with one clock cycle granularity.
Figure 8-27. SPI_CHCTRL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTCLK RESERVED EN
R/W-0h R-0h R/W-
0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 8-14. SPI_CHCTRL Register Field Descriptions
Bit Field Type Reset Description
31-16 RESERVED R 0h
15-8 EXTCLK R/W 0h
Clock ratio extension
This register is used to concatenate with the SPI_CHCONF[CLKD]
register for the clock ratio only when the granularity is one clock
cycle (SPI_CHCONF[CLKG] set to 1). Then, the max value reached
is 4096 clock divider ratio.
0h = Clock ratio is CLKD + 1
1h = Clock ratio is CLKD + 1 + 16
FFh = Clock ratio is CLKD + 1 + 4080
7-1 RESERVED R 0h
0 EN R/W 0h
Channel enable
0h = Channel is not active
1h = Channel is active
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