Texas Instruments CC3235 SimpleLink Series - RGBLCTL Register; RGBLCTL Register Field Descriptions

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SWRU543–January 2019
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Inter-Integrated Sound (I2S) Multichannel Audio Serial Port
12.5.7 RGBLCTL Register (Offset = 60h) [reset = 0h]
RGBLCTL is shown in Figure 12-10 and described in Table 12-12.
Return to Summary Table.
Alias of the global control register (GBLCTL). Writing to the receiver global control register (RGBLCTL)
affects only the receive bits of GBLCTL (bits 4-0). Reads from RGBLCTL return the value of GBLCTL.
RGBLCTL allows the receiver to be reset independently from the transmitter. See Section 3.8 for a
detailed description of GBLCTL.
Figure 12-10. RGBLCTL Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED XFRST XSMRST XSRCLR XHCLKRST XCLKRST
R-0h R-0h R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
RESERVED RFRST RSMRST RSRCLR RHCLKRST RCLKRST
R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 12-12. RGBLCTL Register Field Descriptions
Bit Field Type Reset Description
31-13 RESERVED R 0h
Reserved. The reserved bit location always returns the default value.
A value written to this field has no effect. If writing to this field,
always write the default value for future device compatibility.
12 XFRST R 0h
Transmit frame sync generator reset enable bit. A read of this bit
returns the XFRST bit value of GBLCTL. Writes have no effect.
11 XSMRST R 0h
Transmit state machine reset enable bit. A read of this bit returns the
XSMRST bit value of GBLCTL. Writes have no effect.
10 XSRCLR R 0h
Transmit serializer clear enable bit. A read of this bit returns the
XSRCLR bit value of GBLCTL. Writes have no effect.
9 XHCLKRST R 0h
Transmit high-frequency clock divider reset enable bit. A read of this
bit returns the XHCLKRST bit value of GBLCTL. Writes have no
effect.
8 XCLKRST R 0h
Transmit clock divider reset enable bit. a read of this bit returns the
XCLKRST bit value of GBLCTL. Writes have no effect.
7-5 RESERVED R 0h
Reserved. The reserved bit location always returns the default value.
A value written to this field has no effect. If writing to this field,
always write the default value for future device compatibility.
4 RFRST R/W 0h
Receive frame sync generator reset enable bit. A write to this bit
affects the RFRST bit of GBLCTL.
0h = Receive frame sync generator is reset.
1h = Receive frame sync generator is active.
3 RSMRST R/W 0h
Receive state machine reset enable bit. A write to this bit affects the
RSMRST bit of GBLCTL.
0h = Receive state machine is held in reset.
1h = Receive state machine is released from reset.