Texas Instruments CC3235 SimpleLink Series - SPI_IRQENABLE Register

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SWRU543–January 2019
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SPI (Serial Peripheral Interface)
8.6.4 SPI_IRQENABLE Register (offset = 11Ch) [reset = 0h]
SPI_IRQENABLE is shown in Figure 8-23 and described in Table 8-10.
This register lets the user enable and disable the module internal sources of interrupt, on an event-by-
event basis.
Figure 8-23. SPI_IRQENABLE Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED EOWE WKE
R-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED RX_OVERFLO
W_ENABLE
RX_FULL_ENA
BLE
TX_UNDERFL
OW_ENABLE
TX_EMPTY_E
NABLE
R-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 8-10. SPI_IRQENABLE Register Field Descriptions
Bit Field Type Reset Description
31-18 RESERVED R 0h
17 EOWE R/W 0h
End of word count Interrupt Enable.
0h = Interrupt disabled
1h = Interrupt enabled
16 WKE R/W 0h
Wake-up event interrupt enable in slave mode when an active
control signal is detected on the SPIEN line programmed in the field
SPI_CHCONF[SPIENSLV]
0h = Interrupt disabled
1h = Interrupt enabled
15-4 RESERVED R 0h
3 RX_OVERFLOW_ENABL
E
R/W 0h Receiver register overflow interrupt enable.
0h = Interrupt disabled
1h = Interrupt enabled
2 RX_FULL_ENABLE R/W 0h Receiver register full or almost full interrupt enable.
0h = Interrupt disabled
1h = Interrupt enabled
1 TX_UNDERFLOW_ENAB
LE
R/W 0h Transmitter register underflow interrupt enable.
0h = Interrupt disabled
1h = Interrupt enabled
0 TX_EMPTY_ENABLE R/W 0h
Transmitter register empty or almost empty interrupt enable.
0h = Interrupt disabled
1h = Interrupt enabled