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Timer Registers
335
SWRU543–January 2019
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General-Purpose Timers
9.5.11 GPTMTAMATCHR Register (offset = 30h) [reset = FFFFFFFFh]
GPTMTAMATCHR is shown in Figure 9-15 and described in Table 9-19.
When a 16/32-bit GPTM is configured to one of the 32-bit modes, GPTMTAMATCHR appears as a 32-bit
register (the upper 16 bits correspond to the contents of the GPTM Timer B Match (GPTMTBMATCHR)
register). In a 16-bit mode, the upper 16 bits of this register read as 0s and have no effect on the state of
GPTMTBMATCHR.
Figure 9-15. GPTMTAMATCHR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMR
R/W-FFFFFFFFh
Table 9-19. GPTMTAMATCHR Register Field Descriptions
Bit Field Type Reset Description
31-0 TAMR R/W FFFFFFFFh
GPTM Timer A Match Register. This value is compared to the
GPTMTAR register to determine match events.
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