Texas Instruments CC3235 SimpleLink Series - I2 CSOAR2 Register; I2 CSOAR2 Register Field Descriptions

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SWRU543–January 2019
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Inter-Integrated Circuit (I
2
C) Interface
7.3.21 I2CSOAR2 Register (Offset = 81Ch) [reset = 0h]
I2CSOAR2 is shown in Figure 7-34 and described in Table 7-25.
Return to Summary Table.
This register consists of seven address bits that identify the alternate address for the I2C device on the
I2C bus.
Figure 7-34. I2CSOAR2 Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
OAR2EN OAR2
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-25. I2CSOAR2 Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7 OAR2EN R/W 0h
I2C Slave Own Address 2 Enable
0h = The alternate address is disabled.
1h = Enables the use of the alternate address in the OAR2 field.
6-0 OAR2 R/W 0h
I2C Slave Own Address 2 This field specifies the alternate OAR2
address.