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SHA-MD5 Registers
751
SWRU543–January 2019
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SHA/MD5 Accelerator
19.2.42 DTHE_SHA_IC Register (Offset = 81Ch) [reset = X]
DTHE_SHA_IC is shown in Figure 19-46 and described in Table 19-53.
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SHAMD5 interrupt acknowledge register. Writing 1 to these bits clear the status flag in RIS and MIS
register. Reads are always zero.
Figure 19-46. DTHE_SHA_IC Register
31 30 29 28 27 26 25 24
RESERVED
R-X
23 22 21 20 19 18 17 16
RESERVED
R-X
15 14 13 12 11 10 9 8
RESERVED
R-X
7 6 5 4 3 2 1 0
RESERVED Din Cout Cin
R-X R/WC-0h WC-0h WC-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 19-53. DTHE_SHA_IC Register Field Descriptions
Bit Field Type Reset Description
31-3 RESERVED R X
2 Din R/WC 0h
Clear “input data movement done” flag
1 Cout WC 0h
Clear “output done” flag
0 Cin WC 0h
Clear “input done” flag
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