Texas Instruments CC3235 SimpleLink Series - MCASPCLKCFG0 Register

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SWRU543–January 2019
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Power, Reset, and Clock Management
15.6.38 MCASPCLKCFG0 Register (offset = B0h) [reset = A0000h]
MCASPCLKCFG0 is shown in Figure 15-41 and described in Table 15-41.
Figure 15-41. MCASPCLKCFG0 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED DIVISR
R-0h R/W-Ah
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FRACTN
R/W-0h
Table 15-41. MCASPCLKCFG0 Register Field Descriptions
Bit Field Type Reset Description
31-26 RESERVED R 0h
25-16 DIVISR R/W Ah
MCASP_FRAC_DIV_DIVISOR. If the root clock frequency is Fref
and the required output clock frequency is Freq, the ratio of these
two frequencies (Fref/Freq) can be represented as = I.F where I is
the integer part of the ratio and F is the fractional part of the ratio.
15-0 FRACTN R/W 0h
MCASP_FRAC_DIV_FRACTION. If the root clock frequency is Fref
and the required output clock frequency is Freq, the ratio of these
two frequencies (Fref/Freq) can be represented as = I.F where I is
the integer part of the ratio and F is the fractional part of the ratio.