Texas Instruments CC3235 SimpleLink Series - AES_IV_IN_2 Register; AES_IV_IN_3 Register; AES_IV_IN_2 Register Field Descriptions; AES_IV_IN_3 Register Field Descriptions

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SWRU543–January 2019
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Advance Encryption Standard Accelerator (AES)
17.4.19 AES_IV_IN_2 Register (Offset = 48h) [reset = 0h]
AES_IV_IN_2 is shown in Figure 17-32 and described in Table 17-22.
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Initialization vector input
Figure 17-32. AES_IV_IN_2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-22. AES_IV_IN_2 Register Field Descriptions
Bit Field Type Reset Description
31-0 DATA R/W 0h
IV data
17.4.20 AES_IV_IN_3 Register (Offset = 4Ch) [reset = 0h]
AES_IV_IN_3 is shown in Figure 17-33 and described in Table 17-23.
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Initialization vector input (MSW)
Figure 17-33. AES_IV_IN_3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-23. AES_IV_IN_3 Register Field Descriptions
Bit Field Type Reset Description
31-0 DATA R/W 0h
IV data