I2S Registers
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SWRU543–January 2019
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Inter-Integrated Sound (I2S) Multichannel Audio Serial Port
12.5.9 RFMT Register (Offset = 68h) [reset = 0h]
RFMT is shown in Figure 12-12 and described in Table 12-14.
Return to Summary Table.
The receive bit stream format register (RFMT) configures the receive data format.
Figure 12-12. RFMT Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED RDATDLY
R-0h R/W-0h
15 14 13 12 11 10 9 8
RRVRS RESERVED RPBIT
R/W-0h R-0h R/W-0h
7 6 5 4 3 2 1 0
RSSZ RBUSEL RESERVED
R/W-0h R/W-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 12-14. RFMT Register Field Descriptions
Bit Field Type Reset Description
31-18 RESERVED R 0h
Reserved. The reserved bit location always returns the default value.
A value written to this field has no effect. If writing to this field,
always write the default value for future device compatibility.
17-16 RDATDLY R/W 0h
Receive bit delay.
0h = Reserved
1h = 2-bit delay. The first receive data bit, AXR[n], occurs one
ACLKR cycle after the receive frame sync (AFSR).
2h = Reserved
3h = Reserved
15 RRVRS R/W 0h
Receive serial bitstream order.
0h = Reserved
1h = Bitstream is MSB first. Bit reversal is performed in receive
format bit reverse unit.
14-13 RESERVED R 0h
Reserved. The reserved bit location always returns the default value.
A value written to this field has no effect. If writing to this field,
always write the default value for future device compatibility.
12-8 RPBIT R/W 0h
RPBIT value determines which bit (as read by the CPU or DMA from
RBUF[n]) is used to pad the extra bits. This field only applies when
RPAD = 2h. 0h - 1Fh = Reserved
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