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SWRU543–January 2019
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-M4 Peripherals
3.3.1.19 SYSPRI3 Register (Offset = D20h) [reset = 0h]
SYSPRI3 is shown in Figure 3-19 and described in Table 3-22.
Return to Summary Table.
The SYSPRI3 register configures the priority level, 0 to 7 of the SysTick exception and PendSV handlers.
This register is byte-accessible.
NOTE: This register can only be accessed from privileged mode.
Figure 3-19. SYSPRI3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TICK RESERVED PENDSV RESERVED
R/W-0h R-0h R/W-0h R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED DEBUG RESERVED
R-0h R/W-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 3-22. SYSPRI3 Register Field Descriptions
Bit Field Type Reset Description
31-29 TICK R/W 0h
SysTick Exception Priority
This field configures the priority level of the SysTick exception.
Configurable priority values are in the range 0-7, with lower values
having higher priority.
28-24 RESERVED R 0h
23-21 PENDSV R/W 0h
PendSV Priority
This field configures the priority level of PendSV. Configurable
priority values are in the range 0-7, with lower values having higher
priority.
20-8 RESERVED R 0h
7-5 DEBUG R/W 0h
Debug Priority
This field configures the priority level of Debug. Configurable priority
values are in the range 0-7, with lower values having higher priority.
4-0 RESERVED R 0h
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