Register Description
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SWRU543–January 2019
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Direct Memory Access (DMA)
4.3.4.10 DMA_REQMASKCLR Register (offset = 24h) [reset = 0h]
DMA_REQMASKCLR is shown in Figure 4-16 and described in Table 4-20.
Each bit of this register represents the corresponding DMA channel. Setting a bit clears the corresponding
SET[n] bit in the DMAREQMASKSET register.
Figure 4-16. DMA_REQMASKCLR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLR_n
W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 4-20. DMA_REQMASKCLR Register Field Descriptions
Bit Field Type Reset Description
31-0 CLR_n W 0h Channel [n] Request Mask Clear Bit 0 corresponds to channel 0.
A bit can only be cleared by setting the corresponding CLR[n] bit in
the DMAREQMASKCLR register.
0h = No Effect
1h = Setting a bit clears the corresponding SET[n] bit in the
DMAREQMASKSET register meaning that the peripheral associated
with channel [n] is enabled to request DMA transfers.
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