Texas Instruments CC3235 SimpleLink Series - DES Register Map

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SWRU543–January 2019
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Data Encryption Standard Accelerator (DES)
18.5 DES Registers
Table 18-7 lists the memory-mapped DES registers. All register offset addresses not listed in Table 18-7
should be considered as reserved locations and the register contents should not be modified.
The DES module comprises registers that exist at an offset relative to the DES module base address
0x4403 8000, and a small set of DES μDMA registers that exist at an offset relative to DTHE module base
address 0x4403.0000.
NOTE: The DES registers are limited to 32-bit data accesses; 8- and 16-bit accesses are not
allowed, and can corrupt register contents.
Table 18-7. DES Register Map
Offset Acronym Register Name Section
830h DTHE_DES_IM DES Interrupt Mask Set Register Section 18.5.1
834h DTHE_DES_RIS DES Interrupt Raw Interrupt Status Register Section 18.5.2
838h DTHE_DES_MIS DES Interrupt Masked Interrupt Status Register Section 18.5.3
83Ch DTHE_DES_IC DES Interrupt Clear Interrupt Status Register Section 18.5.4
1000h DES_KEY3_L DES Key 3 LSW for 192-Bit Key Section 18.5.5
1004h DES_KEY3_H DES Key 3 MSW for 192-Bit Key Section 18.5.6
1008h DES_KEY2_L DES Key 2 LSW for 128-Bit Key Section 18.5.7
100Ch DES_KEY2_H DES Key 2 MSW for 128-Bit Key Section 18.5.8
1010h DES_KEY1_L DES Key 1 LSW for 64-Bit Key Section 18.5.9
1014h DES_KEY1_H DES Key 1 MSW for 64-Bit Key Section 18.5.10
1018h DES_IV_L DES Initialization Vector Section 18.5.11
101Ch DES_IV_H DES Initialization Vector Section 18.5.12
1020h DES_CTRL DES Control Section 18.5.13
1024h DES_LENGTH DES Cryptographic Data Length Section 18.5.14
1028h DES_DATA_L DES LSW Data RW Section 18.5.15
102Ch DES_DATA_H DES MSW Data RW Section 18.5.16
1034h DES_SYSCONFIG DES System Configuration Section 18.5.17
103Ch DES_IRQSTATUS DES Interrupt Status Section 18.5.18
1040h DES_IRQENABLE DES Interrupt Enable Section 18.5.19