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I2C Registers
263
SWRU543–January 2019
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Inter-Integrated Circuit (I
2
C) Interface
7.3.27 I2CPC Register (Offset = FC4h) [reset = 1h]
I2CPC is shown in Figure 7-40 and described in Table 7-31.
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The I2CPC register allows software to enable features present in the I2C module.
Figure 7-40. I2CPC Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED HS
R-0h R-1h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-31. I2CPC Register Field Descriptions
Bit Field Type Reset Description
31-1 RESERVED R 0h
0 HS R 1h
High-Speed Capable
0h = The interface is capable of standard or fast mode operation.
1h = Reserved. Must be set to 0
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