Texas Instruments CC3235 SimpleLink Series - DMASWRST Register

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543
SWRU543–January 2019
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Power, Reset, and Clock Management
15.6.13 DMASWRST Register (offset = 4Ch) [reset = 0h]
DMASWRST is shown in Figure 15-16 and described in Table 15-16.
Figure 15-16. DMASWRST Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED ENSTS SWRST
R-0h R-0h R/W-0h
Table 15-16. DMASWRST Register Field Descriptions
Bit Field Type Reset Description
31-2 RESERVED R 0h
1 ENSTS R 0h
UDMA_A_ENABLED_STATUS
0h = UDMA_A clocks and resets are disabled
1h = UDMA_A clocks and resets are enabled
0 SWRST R/W 0h
UDMA_A_SOFT_RESET
0h = Deassert reset for DMA_A
1h = Assert reset for DMA_A