Texas Instruments CC3235 SimpleLink Series - SHAMD5_IDIGEST_E Register; SHAMD5_IDIGEST_E Register Field Descriptions

SHA-MD5 Registers www.ti.com
720
SWRU543–January 2019
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
SHA/MD5 Accelerator
19.2.13 SHAMD5_IDIGEST_E Register (Offset = 30h) [reset = 0h]
SHAMD5_IDIGEST_E is shown in Figure 19-17 and described in Table 19-24.
Return to Summary Table.
WRITE: Inner / Initial Digest [31:0] for SHA-1, [127:96] for SHA-2 / HMAC Key [415:384] for HMAC key
proc
READ: Intermediate / Inner Digest [31:0] for SHA-1, [127:96] for SHA-2 /
Result Digest/MAC [31:0] for SHA-1, [95:64] for SHA-2 224, [127:96] for SHA-2 256
Figure 19-17. SHAMD5_IDIGEST_E Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 19-24. SHAMD5_IDIGEST_E Register Field Descriptions
Bit Field Type Reset Description
31-0 DATA R/W 0h
Data