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Flash Registers
773
SWRU543–January 2019
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On-Chip Parallel Flash
21.5.6 FCMISC Register (Offset = 14h) [reset = 0h]
FCMISC is shown in Figure 21-6 and described in Table 21-7.
Return to Summary Table.
This register provides two functions. First, it reports the cause of an interrupt by indicating which interrupt
source or sources are signaling the interrupt. Second, it serves as the method to clear the interrupt
reporting.
Figure 21-6. FCMISC Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED PROGMISC RESERVED ERMISC INVDMISC RESERVED
R-0h R/W1C-0h R-0h R/W1C-0h R/W1C-0h R-0h
7 6 5 4 3 2 1 0
RESERVED PMISC RESERVED
R-0h R/W1C-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 21-7. FCMISC Register Field Descriptions
Bit Field Type Reset Description
31-14 RESERVED R 0h
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should
be preserved across a read-modify-write operation.
13 PROGMISC R/W1C 0h
PROGVER Masked Interrupt Status and Clear
Writing 1 to this bit clears PROGMISC and also the PROGRIS bit in
the FCRIS register.
0h = When read, 0 indicates that an interrupt has not occurred. A
write of 0 has no effect on the state of this bit.
1h = When read, 1 indicates that an unmasked interrupt was
signaled.
12 RESERVED R 0h
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should
be preserved across a read-modify-write operation.
11 ERMISC R/W1C 0h
ERVER Masked Interrupt Status and Clear
Writing 1 to this bit clears ERMISC and also the ERRIS bit in the
FCRIS register
0h = When read, 0 indicates that an interrupt has not occurred. A
write of 0 has no effect on the state of this bit.
1h = When read, 1 indicates that an unmasked interrupt was
signaled.
10 INVDMISC R/W1C 0h
Invalid Data Masked Interrupt Status and Clear
Writing 1 to this bit clears INVDMISC and also the INVDRIS bit in the
FCRIS register
0h = When read, 0 indicates that an interrupt has not occurred. A
write of 0 has no effect on the state of this bit.
1h = When read, 1 indicates that an unmasked interrupt was
signaled.
9-2 RESERVED R 0h
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should
be preserved across a read-modify-write operation.
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