Flash Registers
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SWRU543–January 2019
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On-Chip Parallel Flash
Table 21-7. FCMISC Register Field Descriptions (continued)
Bit Field Type Reset Description
1 PMISC R/W1C 0h
Programming Masked Interrupt Status and Clear
Writing 1 to this bit clears PMISC and also the PRIS bit in the FCRIS
register
0h = When read, 0 indicates that a programming cycle complete
interrupt has not occurred. A write of 0 has no effect on the state of
this bit.
1h = When read, 1 indicates that an unmasked interrupt was
signaled because a programming cycle completed.
0 RESERVED R 0h
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should
be preserved across a read-modify-write operation.
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