Texas Instruments CC3235 SimpleLink Series - FCIM Register; FCIM Register Field Descriptions

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SWRU543–January 2019
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On-Chip Parallel Flash
21.5.5 FCIM Register (offset = 10h) [reset = 0h]
FCIM is shown in Figure 21-5 and described in Table 21-6.
This register controls whether the flash memory controller generates interrupts to the controller.
Figure 21-5. FCIM Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED PROGMSK RESERVED ERMSK INVDMSK RESERVED
R-0h R-0h R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
RESERVED PMSK RESERVED
R-0h R-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 21-6. FCIM Register Field Descriptions
Bit Field Type Reset Description
31-14 RESERVED R 0h
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should
be preserved across a read-modify-write operation.
13 PROGMSK R 0h
Program Verify Error Interrupt Mask
0h = The PROGRIS interrupt is suppressed and not sent to the
interrupt controller.
1h = An interrupt is sent to the interrupt controller when the
PROGRIS bit is set.
12 RESERVED R 0h
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should
be preserved across a read-modify-write operation.
11 ERMSK R 0h
Erase Verify Error Interrupt Mask
0h = The ERRIS interrupt is suppressed and not sent to the
interrupt controller.
1h = An interrupt is sent to the interrupt controller when the ERRIS
bit is set.
10 INVDMSK R 0h
Invalid Data Interrupt Mask
0h = The INVDRIS interrupt is suppressed and not sent to the
interrupt controller.
1h = An interrupt is sent to the interrupt controller when the
INVDRIS bit is set.
9-2 RESERVED R 0h
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should
be preserved across a read-modify-write operation.
1 PMSK R 0h
Programming Interrupt Mask
This bit controls the reporting of the programming raw interrupt
status to the interrupt controller.
0h = The PRIS interrupt is suppressed and not sent to the interrupt
controller.
1h = An interrupt is sent to the interrupt controller when the PRIS
bit is set.
0 RESERVED R 0h
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should
be preserved across a read-modify-write operation.