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Flash Registers
771
SWRU543–January 2019
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On-Chip Parallel Flash
Table 21-5. FCRIS Register Field Descriptions (continued)
Bit Field Type Reset Description
1 PRIS R 0h
Programming Raw Interrupt Status
This bit provides status on programming cycles which are write or
erase actions generated through the FMC or FMC2 register bits.
This bit is cleared by writing 1 to the PMISC bit in the FCMISC
register.
0h = The programming or erase cycle has not completed.
1h = The programming or erase cycle has completed. This status is
sent to the interrupt controller when the PMASK bit in the FCIM
register is set.
0 RESERVED R 0h
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should
be preserved across a read-modify-write operation.
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