WATCHDOG Registers
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SWRU543–January 2019
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Watchdog Timer
10.3 WATCHDOG Registers
Table 10-1 lists the memory-mapped registers for the watchdog timer? WDT?. All register offset
addresses not listed in Table 10-1 should be considered as reserved locations and the register contents
should not be modified.
Table 10-1 lists the Watchdog registers. The offset listed is a hexadecimal increment to the address of the
register, relative to the watchdog?base address: 0x4000.0000. The WDT module clock must be enabled
before the registers can be programmed.
Table 10-1. WATCHDOG Registers
Offset Acronym Register Name Section
0h WDTLOAD Watchdog Load Section 10.3.1
4h WDTVALUE Watchdog Value Section 10.3.2
8h WDTCTL Watchdog Control Section 10.3.3
Ch WDTICR Watchdog Interrupt Clear Section 10.3.4
10h WDTRIS Watchdog Raw Interrupt Status Section 10.3.5
418h WDTTEST Watchdog Test Section 10.3.6
C00h WDTLOCK Watchdog Lock Section 10.3.7