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Functional Description
349
SWRU543–January 2019
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Watchdog Timer
10.2 Functional Description
The WDT module generates the first time-out signal (interrupt) when the 32-bit counter reaches the zero
state after being enabled. Enabling the counter also enables the WDT interrupt. The WDT can be
configured to reset on the second overflow. The WDT interrupt is maskable.
After the first time-out event, the 32-bit counter is reloaded with the value of the Watchdog Timer Load
(WDTLOAD) register, and the timer resumes counting down from that value. When the WDT has been
configured, the WDTLOCK register is written, which prevents software from inadvertently altering the timer
configuration.
If the timer counts down to its zero state again before the first time-out interrupt is cleared, the WDT
asserts its reset signal to the system. If the interrupt is cleared before the 32-bit counter reaches its
second time-out, the 32-bit counter is loaded with the value in the WDTLOAD register, and counting
resumes from that value.
If the WDTLOAD register is written with a new value while the WDT counter is counting, then the counter
is loaded with the new value, and continues counting.
Writing to the WDTLOAD register does not clear an active interrupt. An interrupt must be specifically
cleared by writing to the Watchdog Interrupt Clear (WDTICR) register.
The WDT is disabled by default out of reset. To achieve maximum watchdog protection of the device, the
WDT can be enabled at the start of the reset vector.
NOTE: In the CC3200 R1 device, TI recommends that the application software, when rebooting after
a WDT reset, requests the PRCM for hibernation (see Section 15.3.9) for 10 ms, and
resumes its full functionality only after returning from this hibernation. This is effective for full
recovery from any complex stuck-at scenario that involves the Wi-Fi
®
subsystem.
NOTE: For CC3220 variants, this step is not needed because it is done by the MCU ROM
bootloader.
The application can determine if the reset cause is WDT by reading the
GPRCM:APPS_RESET_CAUSE[7:0] register (physical address 0×4402 D00C). On wakeup following a
WDT reset, this would read the value 0101.
For more details, refer to .
10.2.1 Initialization and Configuration
The WDT is configured using the following sequence:
1. Enable the peripheral clock by setting the RUNCLKEN bit in the Watchdog Timer Clock Enable
(WDTCLKEN) register.
2. Reset the WDT module using the Watch Dog Timer Software Reset (WDTSWRST) register.
3. Load the WDTLOAD register with the desired timer load value.
4. Set the INTEN bit in the WDTCTL register to enable the WDT, enable interrupts, and lock the control
register.
If the software requires that all of the WDT registers are locked, the WDT module can be fully locked by
writing any value to the WDTLOCK register. To unlock the WDT, write a value of 0x1ACC.E551.
To service the WDT, periodically reload the count value into the WDTLOAD register to restart the count.
The interrupt can be enabled using the INTEN bit in the WDTCTL register to let the processor attempt
corrective action if the WDT is not serviced often enough. The RESEN bit in the WDTCTL register can be
set so that the system resets if the failure is not recoverable using the interrupt service routine (ISR).
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