PRCM APIs
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SWRU543–January 2019
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Power, Reset, and Clock Management
● unsigned long PRCMLPDSWakeupCauseGet(void)
Description: This function gets the LPDS wake-up cause.
Parameter: None
Return: Returns the LPDS wake-up cause enumerated as one of the following:
• PRCM_LPDS_HOST_IRQ: Interrupt from NWP
• PRCM_LPDS_GPIO: LPDS wake-up GPIOs
• PRCM_LPDS_TIMER: Dedicated LPDS timer
● void PRCMLPDSWakeUpGPIOSelect(unsigned long ulGPIOPin, unsigned long ulType)
Description: Sets the specified GPIO as the wake-up source, and configures that GPIO to sense-
specified.
Parameter:
• ulGPIOPin: One of the valid LPDS wake-up GPIOs. ulGPIOPin can be one of the following:
– PRCM_LPDS_GPIO2: GPIO2
– PRCM_LPDS_GPIO4: GPIO4
– PRCM_LPDS_GPIO13: GPIO13
– PRCM_LPDS_GPIO17: GPIO17
– PRCM_LPDS_GPIO11: GPIO11
– PRCM_LPDS_GPIO24: GPIO24
• ulType: Event Type. ulType can be one of the following:
– PRCM_LPDS_LOW_LEVEL: GPIO is held low (0)
– PRCM_LPDS_HIGH_LEVEL: GPIO is held high (1)
– PRCM_LPDS_FALL_EDGE: GPIO changes from high to low
– PRCM_LPDS_RISE_EDGE: GPIO changes from low to high
Return: None
● The user application can put the system in LPDS by invoking the following API function:
void PRCMLPDSEnter(void)
Description: This function puts the system into LPDS power mode, and should be invoked after
configuring the wake source, SRAM retention configuration, and system restore configuration.
Parameter: None
Return: None
15.3.9 Hibernate (HIB)
In this mode, the entire SOC loses its state, including the MCU subsystem, the NWP subsystem, and
SRAM except 2 × 32-bit OCR registers and the free-running slow-clock counter. Core resumes its
execution in the ROM bootloader upon wakeup due to configured wake sources, which include the
following:
• Slow clock counter – Always-on 32.768-kHz counter
• HIB wake-up GPIOs – Six selected GPIOs
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