Timer Registers
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SWRU543–January 2019
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General-Purpose Timers
9.5.10 GPTMTBILR Register (offset = 2Ch) [reset = FFFFh]
GPTMTBILR is shown in Figure 9-14 and described in Table 9-18.
When a GPTM is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are
loaded into the upper 16 bits of the GPTMTAILR register. Reads from this register return the current value
of Timer B, and writes are ignored. In a 16-bit mode, bits 15:0 are used for the load value. Bits 31:16 are
reserved in both cases.
Figure 9-14. GPTMTBILR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TBILR
R/W-FFFFh
Table 9-18. GPTMTBILR Register Field Descriptions
Bit Field Type Reset Description
31-0 TBILR R/W FFFFh
GPTM Timer B Interval Load Register. Writing this field loads the
counter for Timer B. A read returns the current value of
GPTMTBILR. When a 16/32-bit GPTM is in 32-bit mode, writes are
ignored, and reads return the current value of GPTMTBILR.
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