Texas Instruments CC3235 SimpleLink Series - Spi

www.ti.com SPI Registers
299
SWRU543–January 2019
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
SPI (Serial Peripheral Interface)
Table 8-12. SPI_CHCONF Register Field Descriptions (continued)
Bit Field Type Reset Description
5-2 CLKD R/W 0h Frequency divider for SPICLK.
(Only when the module is a master SPI device).
A programmable clock divider divides the SPI reference clock
(CLKSPIREF) with a
4-bit value, and results in a new clock SPICLK available to shift-in
and shiftout data.
0h = 1
1h = 2
2h = 4
3h = 8
4h = 16
5h = 32
6h = 64
7h = 128
8h = 256
9h = 512
Ah = 1024
Bh = 2048
Ch = 4096
Dh = 8192
Eh = 16384
Fh = 32768
1 POL R/W 0h
SPICLK polarity
0h = SPICLK is held high during the active state
1h = SPICLK is held low during the active state
0 PHA R/W 0h
SPICLK phase
0h = Data are latched on odd numbered edges of SPICLK.
1h = Data are latched on even numbered edges of SPICLK.