I2S Registers
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SWRU543–January 2019
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Inter-Integrated Sound (I2S) Multichannel Audio Serial Port
12.5.13 RSTAT Register (Offset = 80h) [reset = 0h]
RSTAT is shown in Figure 12-16 and described in Table 12-18.
Return to Summary Table.
The receiver status register (RSTAT) provides the receiver status and receive TDM time slot number. If
the McASP logic attempts to set an interrupt flag in the same cycle that the CPU writes to the flag to clear
it, the McASP logic has priority and the flag remains set. This also causes a new interrupt request to be
generated.
Figure 12-16. RSTAT Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED RERR
R-0h R/W-0h
7 6 5 4 3 2 1 0
RDMAERR RSTAFRM RDATA RLAST RTDMSLOT RESERVED RSYNCERR ROVRN
R/W-0h R/W-0h R/W-0h R/W-0h R-0h R-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 12-18. RSTAT Register Field Descriptions
Bit Field Type Reset Description
31-9 RESERVED R 0h
Reserved. The reserved bit location always returns the default value.
A value written to this field has no effect. If writing to this field,
always write the default value for future device compatibility.
8 RERR R/W 0h
RERR bit always returns a logic-OR of: ROVRN | RSYNCERR |
RCKFAIL | RDMAERR Allows a single bit to be checked to
determine if a receiver error interrupt has occurred.
0h = No errors have occurred.
1h = An error has occurred.
7 RDMAERR R/W 0h
Receive DMA error flag. RDMAERR is set when the CPU or DMA
reads more serializers through the DMA port in a given time slot than
were programmed as receivers. Causes a receive interrupt (RINT), if
this bit is set and RDMAERR in RINTCTL is set. This bit is cleared
by writing a 1 to this bit. Writing a 0 to this bit has no effect.
0h = Receive DMA error did not occur.
1h = Receive DMA error did occur.
6 RSTAFRM R/W 0h
Receive start of frame flag. Causes a receive interrupt (RINT), if this
bit is set and RSTAFRM in RINTCTL is set. This bit is cleared by
writing a 1 to this bit. Writing a 0 to this bit has no effect.
0h = No new receive frame sync (AFSR) is detected.
1h = A new receive frame sync (AFSR) is detected.
5 RDATA R/W 0h
Receive data ready flag. Causes a receive interrupt (RINT), if this bit
is set and RDATA in RINTCTL is set. This bit is cleared by writing a
1 to this bit. Writing a 0 to this bit has no effect.
0h = No new data in RBUF.
1h = Data is transferred from XRSR to RBUF and ready to be
serviced by the CPU or DMA. When RDATA is set, it always causes
a DMA event (AREVT).
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