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I2S Registers
435
SWRU543–January 2019
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Inter-Integrated Sound (I2S) Multichannel Audio Serial Port
Table 12-18. RSTAT Register Field Descriptions (continued)
Bit Field Type Reset Description
4 RLAST R/W 0h
Receive last slot flag. RLAST is set along with RDATA, if the current
slot is the last slot in a frame. Causes a receive interrupt (RINT), if
this bit is set and RLAST in RINTCTL is set. This bit is cleared by
writing a 1 to this bit. Writing a 0 to this bit has no effect.
0h = Current slot is not the last slot in a frame.
1h = Current slot is the last slot in a frame. RDATA is also set.
3 RTDMSLOT R 0h
Returns the LSB of RSLOT. Allows a single read of RSTAT to
determine whether the current TDM time slot is even or odd.
0h = Current TDM time slot is odd.
1h = Current TDM time slot is even.
2 RESERVED R 0h
Reserved. The reserved bit location always returns the default value.
A value written to this field has no effect. If writing to this field,
always write the default value for future device compatibility.
1 RSYNCERR R/W 0h
Unexpected receive frame sync flag. RSYNCERR is set when a new
receive frame sync (AFSR) occurs before it is expected. Causes a
receive interrupt (RINT), if this bit is set and RSYNCERR in
RINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a
0 to this bit has no effect.
0h = Unexpected receive frame sync did not occur.
1h = Unexpected receive frame sync did occur.
0 ROVRN R/W 0h
Receiver overrun flag. ROVRN is set when the receive serializer is
instructed to transfer data from XRSR to RBUF, but the former data
in RBUF has not yet been read by the CPU or DMA. Causes a
receive interrupt (RINT), if this bit is set and ROVRN in RINTCTL is
set. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit
has no effect.
0h = Receiver overrun did not occur.
1h = Receiver overrun did occur.
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