Texas Instruments CC3235 SimpleLink Series - UARTRSR_UARTECR Register

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SWRU543–January 2019
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Universal Asynchronous Receivers/Transmitters (UARTs)
6.3.2 UARTRSR_UARTECR Register (Offset = 4h) [reset = 0h]
UARTRSR_UARTECR is shown in Figure 6-4 and described in Table 6-4.
Return to Summary Table.
The UARTRSR/UARTECR register is the receive status register/error clear register.
In addition to the UARTDR register, receive status can also be read from the UARTRSR register. If the
status is read from this register, then the status information corresponds to the entry read from UARTDR
prior to reading UARTRSR. The status information for overrun is set immediately when an overrun
condition occurs.
The UARTRSR register cannot be written.
A write of any value to the UARTECR register clears the framing, parity, break, and overrun errors. All the
bits are cleared on reset.
Figure 6-4. UARTRSR_UARTECR Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED OE_OR_DATA BE_OR_DATA PE_OR_DATA FE_OR_DATA
R-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 6-4. UARTRSR_UARTECR Register Field Descriptions
Bit Field Type Reset Description
7-4 DATA W 0h
Error Clear
A write to this register of any data clears the framing, parity, break,
and overrun flags.
31-4 RESERVED R 0h
3 OE_OR_DATA R/W 0h
UART Overrun Error (R) or Error Clear (W)
This bit is cleared by a write to UARTECR. The FIFO contents
remain valid because no further data is written when the FIFO is full,
only the contents of the shift register are overwritten. The CPU must
read the data to empty the FIFO.
0h (R) = No data has been lost due to a FIFO overrun.
1h (R) = New data was received when the FIFO was full, resulting in
data loss.
2 BE_OR_DATA R/W 0h
UART Break Error (R) or Error Clear (W)
This bit is cleared to 0 by a write to UARTECR.
0h (R) = No break condition has occurred
1h (R) = A break condition has been detected, indicating that the
receive data input was held Low for longer than a full-word
transmission time (defined as start, data, parity, and stop bits).
In FIFO mode, this error is associated with the character at the top of
the FIFO. When a break occurs, only one 0 character is loaded into
the FIFO. The next character is only enabled after the receive data
input goes to a 1 (marking state) and the next valid start bit is
received.