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I2C Registers
259
SWRU543–January 2019
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Inter-Integrated Circuit (I
2
C) Interface
7.3.24 I2CFIFOCTL Register (Offset = F04h) [reset = 00040004h]
I2CFIFOCTL is shown in Figure 7-37 and described in Table 7-28.
Return to Summary Table.
The FIFO Control register can be programmed to control various aspects of the FIFO transaction, such as
RX and TX FIFO assignment, byte count value for FIFO triggers, and flushing of the FIFOs.
Figure 7-37. I2CFIFOCTL Register
31 30 29 28 27 26 25 24
RXASGNMT RXFLUSH DMARXENA RESERVED
R/W-0h R/W-0h R/W-0h R-0h
23 22 21 20 19 18 17 16
RESERVED RXTRIG
R-0h R/W-4h
15 14 13 12 11 10 9 8
TXASGNMT TXFLUSH DMATXENA RESERVED
R/W-0h R/W-0h R/W-0h R-0h
7 6 5 4 3 2 1 0
RESERVED TXTRIG
R-0h R/W-4h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 7-28. I2CFIFOCTL Register Field Descriptions
Bit Field Type Reset Description
31 RXASGNMT R/W 0h
RX Control Assignment
0h = RX FIFO is assigned to master
1h = RX FIFO is assigned to slave
30 RXFLUSH R/W 0h
RX FIFO Flush
Setting this bit flushes the RX FIFO. This bit self-clears when the
flush has completed.
29 DMARXENA R/W 0h
DMA RX Channel Enable
0h = DMA RX channel disabled
1h = DMA RX channel enabled
28-19 RESERVED R 0h
18-16 RXTRIG R/W 4h
RX FIFO Trigger
Indicates at what fill level the RX FIFO generates a trigger.
0h = Trigger when RX FIFO contains no bytes
1h = Trigger when Rx FIFO contains 1 or more bytes
2h = Trigger when Rx FIFO contains 2 or more bytes
3h = Trigger when Rx FIFO contains 3 or more bytes
4h = Trigger when Rx FIFO contains 4 or more bytes
5h = Trigger when Rx FIFO contains 5 or more bytes
6h = Trigger when Rx FIFO contains 6 or more bytes
7h = Trigger when Rx FIFO contains 7 or more bytes.
Note: Programming RXTRIG to 0x0 has no effect since no data is
present to transfer out of RX FIFO.
15 TXASGNMT R/W 0h
TX Control Assignment
0h = TX FIFO is assigned to Master
1h = TX FIFO is assigned to Slave
14 TXFLUSH R/W 0h
TX FIFO Flush
Setting this bit flushes the TX FIFO. This bit self-clears when the
flush has completed.
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