Texas Instruments CC3235 SimpleLink Series - Page 260

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SWRU543–January 2019
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Inter-Integrated Circuit (I
2
C) Interface
Table 7-28. I2CFIFOCTL Register Field Descriptions (continued)
Bit Field Type Reset Description
13 DMATXENA R/W 0h
DMA TX Channel Enable
0h = DMA TX channel disabled
1h = DMA TX channel enabled
12-3 RESERVED R 0h
2-0 TXTRIG R/W 4h
TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger is
generated.
0h = Trigger when the TX FIFO is empty.
1h = Trigger when TX FIFO contains 1 byte
2h = Trigger when TX FIFO contains 2 bytes
3h = Trigger when TX FIFO 3 bytes
4h = Trigger when TX FIFO 4 bytes
5h = Trigger when TX FIFO 5 bytes
6h = Trigger when TX FIFO 6 bytes
7h = Trigger when TX FIFO 7 bytes