Texas Instruments CC3235 SimpleLink Series - PSR Register Combinations

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57
SWRU543–January 2019
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Cortex
®
-M4 Processor
2.2.2.2.4 Program Status Register (PSR)
NOTE: This register is also referred to as xPSR.
The Program Status register (PSR) has three functions, and the register bits are assigned to the different
functions:
• Application Program Status register (APSR), bits 31:27, bits 19:16
• Execution Program Status register (EPSR), bits 26:24, bits 15:10
• Interrupt Program Status register (IPSR), bits 7:0
The PSR, IPSR, and EPSR registers can be accessed only in privileged mode; the APSR register can be
accessed in either privileged or unprivileged mode.
APSR contains the current state of the condition flags from previous instruction executions. EPSR
contains the Thumb state bit and the execution state bits for the if-then (IT) instruction or the interruptible-
continuable instruction (ICI) field for an interrupted load multiple or store multiple instruction. Attempts to
read the EPSR directly through application software using the MSR instruction always return zero.
Attempts to write the EPSR using the MSR instruction in application software are always ignored. Fault
handlers can examine the EPSR value in the stacked PSR to determine the operation that faulted.
IPSR contains the exception type number of the current interrupt service routine (ISR).
These registers can be accessed individually, or as a combination of any two or all three registers, using
the register name as an argument to the MSR or MRS instructions. For example, all of the registers can
be read using PSR with the MRS instruction, or APSR only can be written to using APSR with the MSR
instruction. Table 2-3 shows the possible register combinations for the PSR. See the descriptions of the
MRS and MSR instructions in the Cortex
®
-M4 Devices Generic User Guide (ARM DUI 0553A) for more
information about how to access the program status registers.
(1)
The processor ignores writes to the IPSR bits.
(2)
Reads of the EPSR bits return zero, and the processor ignores writes to these bits
Table 2-3. PSR Register Combinations
Register Type Combination
PSR PSR R/W
(1) (2)
APSR, EPSR, and IPSR
IEPSR RO EPSR and IPSR
IAPSR R/W
(1)
APSR and IPSR
EAPSR R/W
(2)
APSR and EPSR
2.2.2.2.5 Priority Mask Register (PRIMASK)
The PRIMASK register prevents activation of all exceptions with programmable priority. Reset,
nonmaskable interrupt (NMI), and hard fault are the only exceptions with fixed priority. Exceptions should
be disabled when they might impact the timing of critical tasks. This register is accessible only in
privileged mode. The MSR and MRS instructions are used to access the PRIMASK register, and the CPS
instruction may be used to change the value of the PRIMASK register. See the Cortex
®
-M4 Devices
Generic User Guide (ARM DUI 0553A) for more information on these instructions.
2.2.2.2.6 Fault Mask Register (FAULTMASK)
The FAULTMASK register prevents activation of all exceptions except for the NMI. Exceptions should be
disabled when they might impact the timing of critical tasks. This register is accessible only in privileged
mode. The MSR and MRS instructions are used to access the FAULTMASK register, and the CPS
instruction may be used to change the value of the FAULTMASK register. See the Cortex
®
-M4 Devices
Generic User Guide (ARM DUI 0553A) for more information on these instructions.