UART Registers
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SWRU543–January 2019
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Universal Asynchronous Receivers/Transmitters (UARTs)
6.3.11 UARTMIS Register (Offset = 40h) [reset = 0h]
UARTMIS is shown in Figure 6-13 and described in Table 6-13.
Return to Summary Table.
The UARTMIS register is the masked interrupt status register. On a read, this register gives the current
masked status value of the corresponding interrupt. A write has no effect.
Figure 6-13. UARTMIS Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED DMATXMIS DMARXMIS
R-0h R-0h R-0h
15 14 13 12 11 10 9 8
RESERVED RESERVED OEMIS BEMIS PEMIS
R-0h R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
FEMIS RTMIS TXMIS RXMIS DSRMIS DCDMIS CTSMIS RIMIS
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 6-13. UARTMIS Register Field Descriptions
Bit Field Type Reset Description
31-18 RESERVED R 0h
17 DMATXMIS R 0h
Transmit DMA Masked Interrupt Status
This bit is cleared by writing a 1 to the DMATXIC bit in the UARTICR
register.
0h = An interrupt has not occurred or is masked.
1h = An unmasked interrupt was signaled due to the completion of
the transmit DMA.
16 DMARXMIS R 0h
Receive DMA Masked Interrupt Status
This bit is cleared by writing a 1 to the DMARXIC bit in the UARTICR
register.
0h = An interrupt has not occurred or is masked.
1h = An unmasked interrupt was signaled due to the completion of
the receive DMA.
15-11 RESERVED R 0h
10 OEMIS R 0h
UART Overrun Error Masked Interrupt Status
This bit is cleared by writing a 1 to the OEIC bit in the UARTICR
register.
0h = An interrupt has not occurred or is masked.
1h = An unmasked interrupt was signaled due to an overrun error.
9 BEMIS R 0h
UART Break Error Masked Interrupt Status
This bit is cleared by writing a 1 to the BEIC bit in the UARTICR
register.
0h = An interrupt has not occurred or is masked.
1h = An unmasked interrupt was signaled due to a break error.
8 PEMIS R 0h
UART Parity Error Masked Interrupt Status
This bit is cleared by writing a 1 to the PEIC bit in the UARTICR
register.
0h = An interrupt has not occurred or is masked.
1h = An unmasked interrupt was signaled due to a parity error.
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