Texas Instruments CC3235 SimpleLink Series - Page 199

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199
SWRU543–January 2019
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Universal Asynchronous Receivers/Transmitters (UARTs)
Table 6-13. UARTMIS Register Field Descriptions (continued)
Bit Field Type Reset Description
7 FEMIS R 0h
UART Framing Error Masked Interrupt Status
This bit is cleared by writing a 1 to the FEIC bit in the UARTICR
register.
0h = An interrupt has not occurred or is masked.
1h = An unmasked interrupt was signaled due to a framing error.
6 RTMIS R 0h
UART Receive Time-Out Masked Interrupt Status
This bit is cleared by writing a 1 to the RTIC bit in the UARTICR
register.
0h = An interrupt has not occurred or is masked.
1h = An unmasked interrupt was signaled due to a receive time out.
5 TXMIS R 0h
UART Transmit Masked Interrupt Status
This bit is cleared by writing a 1 to the TXIC bit in the UARTICR
register or by writing data to the transmit FIFO until it becomes
greater than the trigger level, if the FIFO is enabled, or by writing a
single byte if the FIFO is disabled.
0h = An interrupt has not occurred or is masked.
1h = An unmasked interrupt was signaled due to passing through the
specified transmit FIFO level (if the EOT bit is clear) or due to the
transmission of the last data bit (if the EOT bit is set).
4 RXMIS R 0h
UART Receive Masked Interrupt Status
This bit is cleared by writing a 1 to the RXIC bit in the UARTICR
register or by reading data from the receive FIFO until it becomes
less than the trigger level, if the FIFO is enabled, or by reading a
single byte if the FIFO is disabled.
0h = An interrupt has not occurred or is masked.
1h = An unmasked interrupt was signaled due to passing through the
specified receive FIFO level.
3 DSRMIS R 0h
Reserved
2 DCDMIS R 0h
Reserved
1 CTSMIS R 0h
UART Clear to Send Modem Masked Interrupt Status
This bit is cleared by writing a 1 to the CTSIC bit in the UARTICR
register.
0h = An interrupt has not occurred or is masked.
1h = An unmasked interrupt was signaled due to Clear to Send.
0 RIMIS R 0h
Reserved