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CRC Registers
761
SWRU543–January 2019
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Cyclical Redundancy Check (CRC)
20.3.4 CRCRSLTPP Register (Offset = C18h) [reset = 0h]
CRCRSLTPP is shown in Figure 20-4 and described in Table 20-7.
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This register contains the post-processed CRC result, as configured by the CRCCTRL register.
Figure 20-4. CRCRSLTPP Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSLTPP
RO-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 20-7. CRCRSLTPP Register Field Descriptions
Bit Field Type Reset Description
31-0 RSLTPP RO 0h
Post Processing Result
This register contains the post-processed CRC result.