Register Description
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SWRU543–January 2019
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Direct Memory Access (DMA)
4.3.4.18 DMA_CHASGN Register (offset = 500h) [reset = 0h]
DMA_CHASGN is shown in Figure 4-24 and described in Table 4-28.
Each bit of this register represents the corresponding DMA channel. Setting a bit selects the secondary
channel assignment.
Figure 4-24. DMA_CHASGN Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHASGN_n
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 4-28. DMA_CHASGN Register Field Descriptions
Bit Field Type Reset Description
31-0 CHASGN_n R/W 0h
Channel [n] Assignment Select
0h = Use the primary channel assignment.
1h = Use the secondary channel assignment.
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