DES Registers
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SWRU543–January 2019
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Data Encryption Standard Accelerator (DES)
18.5.1 DTHE_DES_IM Register (Offset = 830h) [reset = Dh]
DTHE_DES_IM is shown in Figure 18-8 and described in Table 18-8.
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The interrupt mask set register lets the user control which interrupt source should interrupt the processor.
Figure 18-8. DTHE_DES_IM Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED Dout Din RESERVED Cin
R-0h R/W-1h R/W-1h R-0h R/W-1h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 18-8. DTHE_DES_IM Register Field Descriptions
Bit Field Type Reset Description
31-4 RESERVED R 0h
3 Dout R/W 1h
Data out: this interrupt is raised when the DMA finishes writing the
last word of the process result.
2 Din R/W 1h
Data in: this interrupt is raised when the DMA writes the last word of
input data to the internal FIFO of the engine.
1 RESERVED R 0h
0 Cin R/W 1h
Context in: this interrupt is raised when the DMA completes context
write to the internal register.
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