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Functional Description
67
SWRU543–January 2019
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Copyright © 2019, Texas Instruments Incorporated
Cortex
®
-M4 Processor
When the processor is executing an exception handler, the exception handler is preempted if a higher
priority exception occurs. If an exception occurs with the same priority as the exception being handled, the
handler is not preempted, irrespective of the exception number. However, the status of the new interrupt
changes to pending.
2.2.4.6 Interrupt Priority Grouping
To increase priority control in systems with interrupts, the NVIC supports priority grouping. This grouping
divides each interrupt priority register entry into two fields:
• An upper field that defines the group priority
• A lower field that defines a subpriority within the group
Only the group priority determines preemption of interrupt exceptions. When the processor is executing an
interrupt exception handler, another interrupt with the same group priority as the interrupt being handled
does not preempt the handler.
If multiple pending interrupts have the same group priority, the subpriority field determines the order in
which they are processed. If multiple pending interrupts have the same group priority and subpriority, the
interrupt with the lowest IRQ number is processed first.
2.2.4.7 Exception Entry and Return
Descriptions of exception handling use the following terms:
• Preemption: When the processor is executing an exception handler, an exception can preempt the
exception handler if its priority is higher than the priority of the exception being handled. See
Section 2.2.4.6 for more information about preemption by an interrupt. When one exception preempts
another, the exceptions are called nested exceptions.
• Return: Return occurs when the exception handler is completed, there is no pending exception with
sufficient priority to be serviced, and the completed exception handler was not handling a late-arriving
exception. The processor pops the stack and restores the processor state to the state it had before the
interrupt occurred.
• Tail-chaining: This mechanism speeds up exception servicing. On completion of an exception handler,
if a pending exception meets the requirements for exception entry, the stack pop is skipped and control
transfers to the new exception handler.
• Late-arriving: This mechanism speeds up preemption. If a higher priority exception occurs during state
saving for a previous exception, the processor switches to handle the higher priority exception and
initiates the vector fetch for that exception. State-saving is not affected by late arrival because the state
saved is the same for both exceptions. Therefore, the state-saving continues uninterrupted. The
processor can accept a late-arriving exception until the first instruction of the exception handler of the
original exception enters the execute stage of the processor. When the late-arriving exception returns
from the exception handler, the normal tail-chaining rules apply.
2.2.4.7.1 Exception Entry
Exception entry occurs when there is a pending exception with sufficient priority and either the processor
is in thread mode or the new exception has a higher priority than the exception being handled, in which
case the new exception preempts the original exception. When one exception preempts another, the
exceptions are nested.
Sufficient priority means the exception has more priority than any limits set by the mask registers (see the
PRIMASK, FAULTMASK, and BASEPRI registers). An exception with less priority than this is pending but
is not handled by the processor. When the processor takes an exception, unless the exception is a tail-
chained or a late-arriving exception, the processor pushes information onto the current stack. This
operation is referred to as stacking, and the structure of eight data words is referred to as stack frame.
Figure 2-6 shows the Cortex
®
-M4 stack frame layout, which is similar to that of Armv7-M implementations
without an FPU.
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