Texas Instruments CC3235 SimpleLink Series - Page 238

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238
SWRU543–January 2019
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Inter-Integrated Circuit (I
2
C) Interface
Table 7-12. I2CMICR Register Field Descriptions (continued)
Bit Field Type Reset Description
4 NACKIC W 0h
Address/Data NACK Interrupt Clear
Writing a 1 to this bit clears the NACKRIS bit in the I2CMRIS register
and the NACKMIS bit in the I2CMMIS register.
A read of this register returns no meaningful data.
3 DMATXIC W 0h
Transmit DMA Interrupt Clear
Writing a 1 to this bit clears the DMATXRIS bit in the I2CMRIS
register and the DMATXMIS bit in the I2CMMIS register.
A read of this register returns no meaningful data.
2 DMARXIC W 0h
Receive DMA Interrupt Clear
Writing a 1 to this bit clears the DMARXRIS bit in the I2CMRIS
register and the DMARXMIS bit in the I2CMMIS register.
A read of this register returns no meaningful data.
1 CLKCIC W 0h
Clock Timeout Interrupt Clear
Writing a 1 to this bit clears the CLKRIS bit in the I2CMRIS register
and the CLKMIS bit in the I2CMMIS register.
A read of this register returns no meaningful data.
0 IC W 0h
Master Interrupt Clear
Writing a 1 to this bit clears the RIS bit in the I2CMRIS register and
the MIS bit in the I2CMMIS register.
A read of this register returns no meaningful data.