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Functional Description
211
SWRU543–January 2019
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Inter-Integrated Circuit (I
2
C) Interface
7.2.3 Interrupts
The I
2
C can generate interrupts when the following conditions are observed in the master module:
• Master transaction completed (RIS bit)
• Master arbitration lost (ARBLOSTRIS bit)
• Master address/data NACK (NACKRIS bit)
• Master bus time-out (CLKRIS bit)
• Next byte request (RIS bit)
• STOP condition on bus detected (STOPRIS bit)
• START condition on bus detected (STARTRIS bit)
• RX DMA interrupt pending (DMARXRIS bit)
• TX DMA interrupt pending (DMATXRIS bit)
• Trigger value for FIFO has been reached and a TX FIFO request interrupt is pending (TXRIS bit)
• Trigger value for FIFO has been reached and a RX FIFO request interrupt is pending (RXRIS bit)
• Transmit (TX) FIFO is empty (TXFERIS bit)
• Receive (RX) FIFO is full (RXFFRIS bit)
Interrupts are generated when the following conditions are observed in the slave module:
• Slave transaction received (DATARIS bit)
• Slave transaction requested (DATARIS bit)
• Slave next byte transfer request (DATARIS bit)
• STOP condition on bus detected (STOPRIS bit)
• START condition on bus detected (STARTRIS bit)
• RX DMA interrupt pending (DMARXRIS bit)
• TX DMA interrupt pending (DMATXRIS bit)
• Programmable trigger value for FIFO has been reached and a TX FIFO request interrupt is pending
(TXRIS bit)
• Programmable trigger value for FIFO has been reached and a RX FIFO request interrupt is pending
(RXRIS bit)
• TX FIFO is empty (TXFERIS bit)
• RX FIFO is full (RXFFRIS bit)
• The I2C master and I2C slave modules have separate interrupt registers. Interrupts can be masked by
clearing the appropriate bit in the I2CMIMR or I2CSIMR registers. The RIS bit in the Master Raw
Interrupt Status (I2CMRIS) register and the DATARIS bit in the Slave Raw Interrupt Status (I2CSRIS)
register have multiple interrupt causes, including a next byte transfer request interrupt. This interrupt is
generated when both master and slave request a receive or transmit transaction.
7.2.4 Loopback Operation
The I2C modules can be placed into an internal loopback mode for diagnostic or debug work by setting
the LPBKbit in the I2C Master Configuration (I2CMCR) register. In loopback mode, the SDA and SCL
signals from the master are tied to the SDA and SCL signals of the slave module, to allow internal testing
of the device without requiring I/O.
7.2.5 FIFO and µDMA Operation
Both the master and the slave modules can access two 8-byte FIFOs used with the µDMA for fast transfer
of data. The TX and RX FIFOs can be independently assigned to either the I2C master or I2C slave.
Thus, the following FIFO assignments are allowed:
• The TX and RX FIFOs can be assigned to the master.
• The TX and RX FIFOs can be assigned to the slave.
• The TX FIFO can be assigned to the master, while the RX FIFO is assigned to the slave, and vice
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