Timer Registers
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SWRU543–January 2019
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General-Purpose Timers
Table 9-12. GPTMCTL Register Field Descriptions (continued)
Bit Field Type Reset Description
3-2 TAEVENT R/W 0h
GPTM Timer A Event Mode. The TAEVENT values are defined as
follows. If PWM output inversion is enabled, edge-detection interrupt
behavior is reversed. Thus, if a positive-edge interrupt trigger has
been set and the PWM inversion generates a positive edge, no
event-trigger interrupt asserts. Instead, the interrupt is generated on
the negative edge of the PWM signal.
0h = Positive edge
1h = Negative edge
2h = Reserved
3h = Both edges
1 TASTALL R/W 0h
GPTM Timer A Stall Enable. The TASTALL values are defined as
follows. If the processor is executing normally, the TASTALL bit is
ignored.
0h = Timer A continues counting while the processor is halted by the
debugger.
1h = Timer A freezes counting while the processor is halted by the
debugger.
0 TAEN R/W 0h
GPTM Timer A Enable. The TAEN values are defined as follows:
0h = Timer A is disabled.
1h = Timer A is enabled and begins counting or the capture logic is
enabled based on the GPTMCFG register.
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