Texas Instruments CC3235 SimpleLink Series - Page 787

www.ti.com DMA_IMR Register (offset = 8Ch) [reset = FF0Fh]
787
SWRU543–January 2019
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CC3235x Device Miscellaneous Registers
Table B-2. DMA_IMR Register Field Descriptions (continued)
Bit Field Type Reset Description
0 SDIOMRD R/W 1h
SDIOM_RD_DMA_DONE_INT_MASK
0h = interrupt enabled
1h = disable corresponding interrupt